package XunChunCPU.WB

import chisel3._
import XunChunCPU.common.CommonConfig._ 
import XunChunCPU.common.Bundles.WBInfo
import XunChunCPU.common.Bundles.RegWriteBundle

class WBReg extends Module {
    val io = IO(new Bundle{
        val wbInfo = Flipped(new WBInfo)
        val write = Flipped(new RegWriteBundle)
    })
    val we = RegInit(false.B)
    val addr = RegInit(0.U(5.W))
    val wdata = RegInit(0.U(32.W))

    we := io.wbInfo.regwe
    addr := io.wbInfo.regAddr
    wdata := io.wbInfo.wData

    io.write.addr := addr
    io.write.wdata := wdata
    io.write.we := we
}